基于at89c51的遙控定時(shí)器外文翻譯

1、<p><b>　　畢業(yè)論文(設(shè)計(jì))</b></p><p><b>　　文獻(xiàn)翻譯</b></p><p>　　本翻譯源自于： CNKI數(shù)字圖書館 </p><p>　　畢業(yè)設(shè)計(jì)名稱：基于單片機(jī)的無(wú)線定時(shí)計(jì)時(shí)系統(tǒng)接口設(shè)計(jì)</p><p>　　外文翻譯名

2、稱： 基于單片機(jī)的定時(shí)器設(shè)計(jì) </p><p>　　學(xué) 生 姓 名 ： 魏巍 </p><p>　　院 (系)： 電子信息學(xué)院 </p><p>　　專 業(yè) 班 級(jí) ： 電氣10703班

3、 </p><p>　　指 導(dǎo) 教 師 ： 高秀娥 </p><p>　　輔 導(dǎo) 教 師 ： 高秀娥 </p><p>　　時(shí) 間 ： 2011年2月21日 至 2011年4月20日 </p>&

4、lt;p>　　基于AT89C51的遙控定時(shí)器</p><p>　　電氣10703班魏巍譯</p><p><b>　　描述：</b></p><p>　　AT89C51是一個(gè)低電壓，高性能CMOS 8位單片機(jī)帶有4K字節(jié)的可反復(fù)擦寫的程序存儲(chǔ)器（PENROM）。這種器件采用ATMEL公司的高密度、不容易丟失存儲(chǔ)技術(shù)生產(chǎn)，并且能夠與MCS-

5、51系列的單片機(jī)兼容。片內(nèi)含有8位中央處理器和閃爍存儲(chǔ)單元，有較強(qiáng)的功能的AT89C51單片機(jī)能夠被應(yīng)用到控制領(lǐng)域中。</p><p><b>　　功能特性：</b></p><p>　　AT89C51提供以下的功能標(biāo)準(zhǔn)：4K字節(jié)閃爍存儲(chǔ)器，128字節(jié)隨機(jī)存取數(shù)據(jù)存儲(chǔ)器，32個(gè)I/O口，2個(gè)16位定時(shí)/計(jì)數(shù)器，1個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，1個(gè)串行通信口，片內(nèi)震蕩器和時(shí)鐘電

6、路。另外，AT89C51還可以進(jìn)行0HZ的靜態(tài)邏輯操作，并支持兩種軟件的節(jié)電模式。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)存儲(chǔ)器、定時(shí)/計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存隨機(jī)存取數(shù)據(jù)存儲(chǔ)器中的內(nèi)容，但震蕩器停止工作并禁止其它所有部件的工作直到下一個(gè)復(fù)位。</p><p><b>　　引腳描述：</b></p><p>　　VCC：電源電壓

7、 </p><p><b>　　GND：地</b></p><p><b>　　P0口：</b></p><p>　　P0口是一組8位漏極開路雙向I/O口，即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口時(shí)，每一個(gè)管腳都能夠驅(qū)動(dòng)8個(gè)TTL電路。當(dāng)“1”被寫入P0口時(shí)，每個(gè)管腳都能夠作為高阻抗輸入端。P0口還能夠在訪問外部數(shù)據(jù)存儲(chǔ)器或程

8、序存儲(chǔ)器時(shí)，轉(zhuǎn)換地址和數(shù)據(jù)總線復(fù)用，并在這時(shí)激活內(nèi)部的上拉電阻。P0口在閃爍編程時(shí)，P0口接收指令，在程序校驗(yàn)時(shí)，輸出指令，需要接電阻。</p><p><b>　　P1口：</b></p><p>　　P1口一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)4個(gè)TTL電路。對(duì)端口寫“1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)可作為輸入口。因?yàn)閮?nèi)部有電阻，某

9、個(gè)引腳被外部信號(hào)拉低時(shí)輸出一個(gè)電流。閃爍編程時(shí)和程序校驗(yàn)時(shí)，P1口接收低8位地址。</p><p><b>　　P2口：</b></p><p>　　P2口是一個(gè)內(nèi)部帶有上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)4個(gè)TTL電路。對(duì)端口寫“1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)，可作為輸入口。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流。在訪問外部

10、程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口線上的內(nèi)容在整個(gè)運(yùn)行期間不變。閃爍編程或校驗(yàn)時(shí)，P2口接收高位地址和其它控制信號(hào)。</p><p><b>　　P3口：</b></p><p>　　P3口是一組帶有內(nèi)部電阻的8位雙向I/O口，P3口輸出緩沖故可驅(qū)動(dòng)4個(gè)TTL電路。對(duì)P3口寫如“1”時(shí)，它們被內(nèi)

11、部電阻拉到高電平并可作為輸入端時(shí)，被外部拉低的P3口將用電阻輸出電流。</p><p>　　P3口除了作為一般的I/O口外，更重要的用途是它的第二功能，如下表所示：</p><p>　　P3口還接收一些用于閃爍存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。</p><p><b>　　RST：</b></p><p>　　復(fù)位輸入。當(dāng)

12、震蕩器工作時(shí)，RET引腳出現(xiàn)兩個(gè)機(jī)器周期以上的高電平將使單片機(jī)復(fù)位。</p><p><b>　　ALE/PROG:</b></p><p>　　當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ALE以時(shí)鐘震蕩頻率的1/16輸出固定的正脈沖信號(hào)，因此它可對(duì)輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳

13、過一個(gè)ALE脈沖</p><p>　　時(shí)，閃爍存儲(chǔ)器編程時(shí)，這個(gè)引腳還用于輸入編程脈沖。如果必要，可對(duì)特殊寄存器區(qū)中的</p><p>　　8EH單元的D0位置禁止ALE操作。這個(gè)位置后只有一條MOVX和MOVC指令A(yù)LE才會(huì)</p><p>　　被應(yīng)用。此外，這個(gè)引腳會(huì)微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無(wú)效。</p><p>&l

14、t;b>　　PSEN：</b></p><p>　　程序儲(chǔ)存允許輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C51由外部程序存儲(chǔ)器讀取指令時(shí)，每個(gè)機(jī)器周期兩次PSEN 有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，這兩次有效的PSEN 信號(hào)不出現(xiàn)。</p><p><b>　　EA/VPP：</b></p><p>

15、　　外部訪問允許。欲使中央處理器僅訪問外部程序存儲(chǔ)器，EA端必須保持低電平。需要注意的是：如果加密位LBI被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平，CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。閃爍存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電壓VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP。</p><p>　　XTAL1：震蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。</p><p>

16、;　　XTAL2：震蕩器反相放大器的輸出端。</p><p>　　掉電和空閑模式下的WDT：</p><p>　　掉電時(shí)期，晶體振蕩停止，看門狗定時(shí)器也停止。掉電模式下，用戶不嗯那個(gè)在復(fù)位看門狗定時(shí)器。有兩種方法可以推出掉電模式：硬件復(fù)位或通過激活外部中斷，當(dāng)硬件復(fù)位退出掉電模式時(shí)，處理看門狗定時(shí)器可像通常的上電復(fù)位一樣。當(dāng)由中斷退出掉電模式時(shí)則有所不同，中斷低電平狀態(tài)持續(xù)到晶體振蕩穩(wěn)定，

17、當(dāng)中斷電平變?yōu)楦唠娖绞录纯上鄳?yīng)中斷服務(wù)。以防止中斷誤復(fù)位，當(dāng)器件復(fù)位，中斷引腳持續(xù)為低時(shí)，看門狗定時(shí)器并未開始計(jì)數(shù)，知道中斷引腳被拉高時(shí)為止。這為在掉電模式下的中斷執(zhí)行中斷服務(wù)程序而設(shè)置。為保證看門狗定時(shí)器在退出掉電模式時(shí)極端情況下不溢出，最好在進(jìn)入掉電模式前復(fù)位看門狗定時(shí)器。在進(jìn)入空閑模式前，看門狗定時(shí)器打開時(shí)，WDT是否繼續(xù)計(jì)數(shù)由SFR中的AUXR的WDIDLE位決定，在IDLE期間（位WDIDLE=0）默認(rèn)狀態(tài)是繼續(xù)計(jì)數(shù)。為防止A

18、T89S51從空閑模式中復(fù)位，用戶應(yīng)該周期性地設(shè)置定時(shí)器，重新進(jìn)入空閑模式。</p><p>　　當(dāng)WDIDLE位被置位，在空閑模式中看門狗定時(shí)器將停止計(jì)數(shù)，直到從空閑(IDLE)模式中退出重新開始計(jì)數(shù)。</p><p><b>　　中斷：</b></p><p>　　AT89S51共有五個(gè)中斷向量：兩個(gè)外部中斷（ INT0和INT1 ） ，兩

19、個(gè)定時(shí)器中斷（Timer0和Timer1)和一個(gè)串行中斷。這些中斷源各自的禁止和使能位參見特殊功能寄存器的IE。IE也包含總中斷控制位EA，EA清0，將關(guān)閉所中斷。</p><p><b>　　空閑模式：</b></p><p>　　在空閑工作模式狀態(tài)， CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍然保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)特

20、那個(gè)保持不變，空閑模式可由任何語(yǔ)序中斷的請(qǐng)求或硬件復(fù)位終止。</p><p>　　需要注意的是，當(dāng)由硬件復(fù)位來終止空閑工作模式時(shí)，CPU通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期有效，在這種情況下，內(nèi)部禁止CPU訪問片內(nèi)RAM,而允許訪問其他端口。為了避免在復(fù)位結(jié)束時(shí)可能對(duì)端口產(chǎn)生意外寫入，激活空閑模式的那條指令的后一條指令不應(yīng)該是一條對(duì)端口或外

21、部存儲(chǔ)器的寫入指令。掉電模式：</p><p>　　在掉線模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的方法是硬件復(fù)位或由處于使能狀態(tài)的外中斷INT0和INT1激活。復(fù)位后將重新定義全部特殊功能寄存器，但不改變?cè)瓉鞷AM中的內(nèi)容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無(wú)效，且必須保持一定時(shí)間以使振蕩器重啟動(dòng)并穩(wěn)定工作。<

22、/p><p>　　表8-1 空閑和掉電期間外部引腳狀態(tài)</p><p><b>　　時(shí)鐘震蕩器：</b></p><p>　　AT89C51中有一個(gè)用于構(gòu)成內(nèi)部震蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自然震蕩器。 外接石英晶體及電容C1，C2接在

23、放大器的反饋回路中構(gòu)成并聯(lián)震蕩電路。對(duì)外接電容C1，C2雖然沒有十分嚴(yán)格的要求，但電容容量的大小會(huì)輕微影響震蕩頻率的高低、震蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性。如果使用石英晶體，我們推薦電容使用30PF±10PF，而如果使用陶瓷振蕩器建議選擇40PF±10PF。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖示。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。由于外部時(shí)鐘

24、信號(hào)是通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。</p><p>　　內(nèi)部振蕩電路 外部振蕩電路定時(shí)器：</p><p>　　8位的倒計(jì)數(shù)器（地址0FH）由定時(shí)器控制寄存器（地址0EH，參見表25）控制，定時(shí)器控制寄存器用

25、于設(shè)定定時(shí)器的頻率（4096，64，1，或1/60Hz），以及設(shè)定定時(shí)器有效或無(wú)效。定時(shí)器從軟件設(shè)置的8位二進(jìn)制數(shù)倒計(jì)數(shù)，每次倒計(jì)數(shù)結(jié)束，定時(shí)器設(shè)置標(biāo)志位TF（參見表7），定時(shí)器標(biāo)志位TF只可以用軟件清除，TF用于產(chǎn)生一個(gè)中斷（/INT），每個(gè)倒計(jì)數(shù)周期產(chǎn)生一個(gè)脈沖作為中斷信號(hào)。TI/TP控制中斷產(chǎn)生的條件。當(dāng)讀定時(shí)器時(shí)，返回當(dāng)前倒計(jì)數(shù)的數(shù)值。</p><p>　　CLKOUT時(shí)鐘輸出：</p>&

26、lt;p>　　管腳CLKOUT可以輸出可編程的方波。CLKOUT頻率寄存器，決定方波的頻率，CLKOUT可以輸出32.768KHz(缺省值)，1024，32，1Hz的方波。CLKOUT為開漏輸出管腳，通電時(shí)有效，無(wú)效時(shí)為高阻抗。</p><p><b>　　石英晶片頻：</b></p><p><b>　　方法１：</b></p>

27、;<p>　　定值OSCI電容――計(jì)算所需的電容平均值，用此值的定值電容，通電后在CLKOUT管腳上測(cè)出的頻率應(yīng)為32.768kHz，測(cè)出的頻率值偏差去取決于石英晶片，電容偏差和器件之間的偏差（平均為±5×10-6）。平均偏差可達(dá)5分鐘／年</p><p><b>　　方法２：</b></p><p>　　OSCI微調(diào)電容――可通過調(diào)

28、整OSCI管腳的微調(diào)電容使振蕩器頻率達(dá)到精確值，這時(shí)可測(cè)出通電時(shí)管腳CLKOUT上的32.768kHz信號(hào)。</p><p><b>　　方法3：</b></p><p>　　OSCI輸出—直接測(cè)量管腳OSCI的輸出。</p><p>　　Design of AT89C51 Special-Purpose Timer</p>&l

29、t;p>　　Description：</p><p>　　The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured usin

30、g Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conven

31、tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip</p><p>　　Function characteristic：</p><p>　　The AT89C51 provides the following standard fe

32、atures: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT

33、89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interr

34、upt system to </p><p>　　Pin Description：</p><p>　　VCC：Supply voltage.</p><p>　　GND：Ground.</p><p><b>　　Port 0：</b></p><p>　　Port 0 is an 8-bit

35、open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiple

36、xed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during progr

37、amverification. External pullups are requ</p><p><b>　　Port 1：</b></p><p>　　Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source

38、four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of t

39、he internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p><b>　　Port 2：</b></p><p>　　Port 2 is an 8-bit bi-directional I/O

40、 port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that

41、are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that u

42、se 16-bit addresses. In</p><p><b>　　Port 3：</b></p><p>　　Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.Wh

43、en 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3

44、also serves the functions of various special features of the AT89C51 as listed below:</p><p>　　Port 3 also receives some control signals for Flash programming and verification.</p><p><b>

45、　　RST：</b></p><p>　　Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.</p><p><b>　　ALE/PROG：</b></p><p>　　Ad

46、dress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at

47、a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.</p><p>　　If

48、 desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit </p><p>　　set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setti

49、ng the ALE-disable bit has no effect if the microcontroller is in external execution mode.</p><p><b>　　PSEN：</b></p><p>　　Program Store Enable is the read strobe to external program

50、memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.</p><

51、p><b>　　EA/VPP：</b></p><p>　　External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.

52、 Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) dur

53、ing Flash programming, for parts that require12-volt VPP.</p><p><b>　　XTAL1：</b></p><p>　　Input to the inverting oscillator amplifier and input to the internal clock operating circui

54、t.</p><p><b>　　XTAL2：</b></p><p>　　Output from the inverting oscillator amplifier.</p><p>　　WDT DURING Power-down and Idle</p><p>　　In Power-down mode the o

55、scillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated externa

56、l interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an

57、 interrupt is significantly differen</p><p>　　With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.</p><p>　　5.Interrupts</p><p&g

58、t;　　The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 6-1. Each of

59、these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.</p>&

60、lt;p>　　Idle Mode </p><p>　　In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special f

61、unction registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. </p><p>　　Note that when idle mode is terminated by a hardware reset, the

62、 device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access t

63、o the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to<

64、;/p><p>　　Power-down Mode</p><p>　　In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Funct

65、ion Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset red

66、efines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its n</p><p>　　Table Status of External Pins During Idle and Power-down Modes</p><

67、p>　　Oscillator Characteristics</p><p>　　XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Eith

68、er a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty c

69、ycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two fli</p><p>　　Figure 1. Oscillator Connections Figure 2. External Clock Drive Configur

70、ation</p><p><b>　　Timer</b></p><p>　　8 counters but actually (address 0FH) by the timer control register (address 0EH, see also Table 25) to control, decides when the control registe

71、r uses in establishing timer's frequency (4096,64,1, either 1/60Hz), as well as hypothesis timer effective or invalid. Timer 8 binary numbers which establishes from the software count but actually, each time but actu

72、ally counted finishes, the timer established flag bit TF (to see also Table 7), timer flag bit TF only might use the software to eliminate,</p><p>　　The CLKOUT clock outputs</p><p>　　Base pin CL

73、KOUT may output the programmable square-wave. CLKOUT frequency register the decision square-wave frequency, CLKOUT may output 32.768KHz (default value), 1024,32,1Hz square-wave. CLKOUT is opens leaks outputs the base pi

74、n, when the circular telegram effective, is invalid when is the high impedance.</p><p>　　Method 1: the definite value OSCI electric capacity - computation needs electric capacity mean value, with this value

75、definite value electric capacity, after the circular telegram, determines the frequency characteristic on the CLKOUT base pin is 32.768kHz, determines the frequency value deviation is decided by the quartz chip, between

76、the electric capacity deviation and component's deviation (average for ±5×10-6). The average deviation may reach 5 minute/year</p><p>　　Method 2: the OSCI trimming electric capacity - may throu

77、gh adjust the OSCI base pin's trimming electric capacity to enable the oscillator frequency to achieve the precise value, by now was observable when the circular telegram on base pin CLKOUT 32.768kHz signal</p>