at89c51的介紹外文翻譯1

1、<p>　　AT89C51的介紹</p><p><b>　　描述：</b></p><p>　　AT89C51是一個(gè)低電壓，高性能CMOS8位單片機(jī)帶有4K字節(jié)的可反復(fù)擦寫的程序存儲(chǔ)器（PENROM）。和128字節(jié)的存取數(shù)據(jù)存儲(chǔ)器（RAM），這種器件采用ATMEL公司的高密度、不容易丟失存儲(chǔ)技術(shù)生產(chǎn)，并且能夠與MCS-51系列的單片機(jī)兼容。片內(nèi)含有8位中央

2、處理器和閃爍存儲(chǔ)單元，功能強(qiáng)大AT89C51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場合，可靈活應(yīng)用于各種控制領(lǐng)域。</p><p><b>　　主要性能參數(shù)：</b></p><p>　　·與MCS-51產(chǎn)品指令系統(tǒng)完全兼容</p><p>　　·4K字節(jié)可重擦寫Flash閃速存儲(chǔ)器</p><p>　　

3、·1000次擦寫周期</p><p>　　·數(shù)據(jù)保留時(shí)間：10年</p><p>　　·全靜態(tài)操作：0Hz—24MHz</p><p>　　·三級(jí)加密程序存儲(chǔ)器</p><p>　　·128×8字節(jié)內(nèi)部RAM</p><p>　　·32個(gè)可編程I/O

4、口線</p><p>　　·2個(gè)16位定時(shí)/計(jì)數(shù)器</p><p><b>　　·6個(gè)中斷源</b></p><p>　　·可編程串行UART通道</p><p>　　·低功耗空閑和掉電模式</p><p>　　·片內(nèi)振蕩器和時(shí)鐘電路</p&

5、gt;<p>　　·全雙工UART串行中斷口線</p><p><b>　　·雙數(shù)據(jù)寄存器指針</b></p><p><b>　　功能特性概述：</b></p><p>　　AT89C51提供以下標(biāo)準(zhǔn)功能：4K字節(jié)Flash閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM，32個(gè)I/O口線，兩個(gè)16位定

6、時(shí)/計(jì)數(shù)器，一個(gè)5向量兩級(jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89C51可降至0Hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式。空閑方式停止CPU的工作，但允許RAM，定時(shí)/計(jì)數(shù)器。串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。</p><p>　　AT89C51單片機(jī)是一個(gè)行業(yè)標(biāo)準(zhǔn)架構(gòu)，被廣泛接受和應(yīng)用，并作

7、為一種開發(fā)工具。有許多工業(yè)供應(yīng)商，他們供應(yīng)這種控制器或把這種控制器集成到某種類型的系統(tǒng)芯片的結(jié)構(gòu)。醫(yī)學(xué)研究理事會(huì)和高級(jí)微電子研究所都選擇這個(gè)設(shè)備，但他們論證的是兩種截然不同固化工藝。醫(yī)學(xué)研究理事會(huì)的實(shí)例是使用時(shí)間鎖存，需要具體時(shí)間以確保單粒子效應(yīng)減少到最低限度。高級(jí)微電子研究所采用超低功耗，以及布局和建筑固化工藝的設(shè)計(jì)原則來實(shí)現(xiàn)其結(jié)果。這些是與Aeroflex聯(lián)合技術(shù)微電子中心（ UTMC ）完全不同的方法 ，抗輻射固化的AT89C51

8、的工業(yè)供應(yīng)商，利用抗輻射固化進(jìn)程研制自己的AT89C51單片機(jī)。</p><p><b>　　引腳功能說明：</b></p><p><b>　　·VCC：電源電壓</b></p><p><b>　　·GND：地</b></p><p>　　·P

9、0口：P0口是一組8位漏極開路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端口寫“1”可作為高阻抗輸入端用。</p><p>　　在訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間即或內(nèi)部上拉電阻。</p><p>　　在Flash編程時(shí)，P0口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)

10、，校驗(yàn)時(shí)，要求外接上拉電阻。</p><p>　　·P1口：P1是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。</p><p>　　Flash編程和程序校驗(yàn)期間，P1接

11、收低8位地址。</p><p>　　·P2口：P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。</p><p>　　在訪問外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器（

12、例如執(zhí)行MOVX@DPTR指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲(chǔ)器（如執(zhí)行MOVX@RI指令）時(shí)，P2口線上的內(nèi)容在整個(gè)訪問期間不改變。</p><p>　　Flash編程或檢驗(yàn)時(shí)，P2亦接收高位地址和其它控制信號(hào)。</p><p>　　·P3口：P3口是一組帶有內(nèi)部電阻的8位雙向I/O口，P3口輸出緩沖故可驅(qū)動(dòng)4個(gè)TTL電路。當(dāng)P3口寫入“1”后，它們

13、被內(nèi)部上拉為高電平，并用作輸入。作為輸入，由于外部下拉為低電平，P3口將輸出電流（ILL）這是由于上拉的緣故。</p><p>　　P3口除了作為一般的I/O口外，更重要的用途是它的第二功能，如表1所示：</p><p>　　表1 P3口第二功能</p><p>　　P3口還接收一些用于閃爍存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。</p><p>　

14、　·RET：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RET引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。</p><p>　　·ALE/：當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（）。即使不訪問外部存儲(chǔ)器，ALE仍以時(shí)鐘振蕩頻率的1/6輸出固定的正脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：

15、每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ALE脈沖。</p><p>　　如有必要，可通過對(duì)特殊功能寄存器（SFR）區(qū)中的8EH單元的D0位置位，可禁止ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無效。</p><p>　　·：程序儲(chǔ)存允許（）輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C51由外部

16、程序存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器，這兩次有效的信號(hào)不出現(xiàn)。</p><p>　　/VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲(chǔ)器（地址為0000H—FFFFH），端必須保持低電平（接地）。需注意的是：如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如端為高電平（接VCC端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。當(dāng)保持低電平時(shí)，則在此期間外

17、部程序存儲(chǔ)器（0000H-FFFFH），不管是否有內(nèi)部程序存儲(chǔ)器。</p><p>　　Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電源VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP。</p><p>　　XTAL1：振蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。</p><p>　　XTAL2：振蕩器反相放大器的輸出端。</p><p

18、>　　Ready/：字節(jié)編程的進(jìn)度可通過RDY/輸出信號(hào)監(jiān)測，編程期間，ALE變?yōu)楦唠娖健癏”后P3.4（RDY/）端電平被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，P3.4變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀態(tài)。</p><p><b>　　振蕩器特性：</b></p><p>　　XTAL1和XTAL2分別為反向放大器的輸入和輸出。該反向放大器可以配置為片內(nèi)振蕩器。

19、石晶振蕩和陶瓷振蕩均可采用。如采用外部時(shí)鐘源驅(qū)動(dòng)器件，XTAL2應(yīng)不接。有余輸入至內(nèi)部時(shí)鐘信號(hào)要通過一個(gè)二分頻觸發(fā)器，因此對(duì)外部時(shí)鐘信號(hào)的脈寬無任何要求，但必須保證脈沖的高低電平要求的寬度。</p><p><b>　　時(shí)鐘振蕩器：</b></p><p>　　AT89C51中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端

20、和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體 或陶瓷諧振器一起構(gòu)成自激振蕩器。</p><p>　　用戶也可以采用外部時(shí)鐘。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。</p><p>　　由于外部時(shí)鐘信號(hào)是通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)

21、條件的要求。</p><p><b>　　空閑節(jié)電模式：</b></p><p>　　在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。</p><p>　　通過硬件復(fù)位也可將空閑工作模式終止。需要注意的是：

22、當(dāng)由硬件復(fù)位來終止空閑工作模式時(shí)，CPU通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期有效，在這種情況下，內(nèi)部禁止CPU訪問片內(nèi)RAM，而允許訪問其它端口。為了避免可能對(duì)端口產(chǎn)生意外寫入，激活空閑模式的那條指令后一條指令不應(yīng)是一條對(duì)端口或外部存儲(chǔ)器的寫入指令。</p><p><b>　　掉電模式：</b></p>

23、<p>　　在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時(shí)間以使振蕩器重啟動(dòng)并穩(wěn)定工作。</p><p>　　Flash閃速存儲(chǔ)器的編程：</p><p

24、>　　AT89C51單片機(jī)內(nèi)部有4K字節(jié)的Flash PEROM，這個(gè)Flash存儲(chǔ)陣列出廠時(shí)已處于擦除狀態(tài)（即所有存儲(chǔ)單元的內(nèi)容均為FFH），用戶隨時(shí)可對(duì)其進(jìn)行編程。編程接口可接收高電壓（+12V）或低電壓（VCC）的允許編程信號(hào)。低電壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用EPROM編程器兼容。</p><p>　　AT89C51的程序存儲(chǔ)器陣列是采用字節(jié)寫入方式編程的，每次寫入一個(gè)字

25、節(jié)，要對(duì)整個(gè)芯片內(nèi)的PEROM程序存儲(chǔ)器寫入一個(gè)非空字節(jié)，必須使用片擦除的方式將整個(gè)存儲(chǔ)器的內(nèi)容清除。</p><p><b>　　編程方法：</b></p><p>　　編程前，須根據(jù)表設(shè)置好地址、數(shù)據(jù)及控制信號(hào)。AT89C51編程方法如下：</p><p>　　1、在地址線上加上要編程單元的地址信號(hào)。</p><p>

26、;　　2、在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。</p><p>　　3、激活相應(yīng)的控制信號(hào)。</p><p>　　4、在高電壓編程方式時(shí)，將EA/VPP端加上+12V編程電壓。</p><p>　　5、每對(duì)Flash存儲(chǔ)陣列寫入一個(gè)字節(jié)或每寫入一個(gè)程序加密位，加上一個(gè)ALE/編程脈沖。改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)1—5步驟，直到全部文件編程結(jié)束。每個(gè)字節(jié)寫入周期

27、是自身定時(shí)的，通常約為1.5ms。</p><p><b>　　數(shù)據(jù)查詢：</b></p><p>　　AT89C51單片機(jī)用數(shù)據(jù)查詢方式來檢測一個(gè)寫周期是否結(jié)束，在一個(gè)寫周期中，如需讀取最后寫入的那個(gè)字節(jié)，則讀出的數(shù)據(jù)最高位是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數(shù)據(jù)就會(huì)出現(xiàn)在所有輸出端上，此時(shí)，可進(jìn)入下一個(gè)字節(jié)的寫周期，寫周期開始后，可在任意時(shí)刻進(jìn)行數(shù)據(jù)查

28、詢。</p><p><b>　　程序校驗(yàn)：</b></p><p>　　如果加密位LB1、LB2沒有進(jìn)行編程，則代碼數(shù)據(jù)可通過地址和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)。加密位不可直接校驗(yàn)，加密位的校驗(yàn)可通過對(duì)存儲(chǔ)器的校驗(yàn)和寫入狀態(tài)來驗(yàn)證。</p><p><b>　　芯片擦除：</b></p><p>　　整

29、個(gè)PEROM陣列和三個(gè)鎖定位的電擦除可通過正確的控制信號(hào)組合，并保持ALE管腳處于低電平10ms 來完成。在芯片擦操作中，代碼陣列全被寫“1”且在任何非空存儲(chǔ)字節(jié)被重復(fù)編程以前，該操作必須被執(zhí)行。 </p><p>　　此外，AT89C51設(shè)有穩(wěn)態(tài)邏輯，可以在低到零頻率的條件下靜態(tài)邏輯，支持兩種軟件可選的掉電模式。在閑置模式下，CPU停止工作。但RAM，定時(shí)器，計(jì)數(shù)器，串口和中斷系統(tǒng)仍在工作。在掉電模式下，保存R

30、AM的內(nèi)容并且凍結(jié)振蕩器，禁止所用其他芯片功能，直到下一個(gè)硬件復(fù)位為止。</p><p><b>　　讀片內(nèi)簽名字節(jié)：</b></p><p>　　讀簽名字節(jié)的過程和單元030H、031H及032H的正常校驗(yàn)相仿，只需將P3.6和P3.7保持低電平，返回值意義如下：</p><p>　　(030H)=1EH聲明產(chǎn)品由ATMEL公司制造</

31、p><p>　　(031H)=51H聲明為AT89C51單片機(jī)</p><p>　　(032H)=FFH聲明為12V編程電壓</p><p>　　(032H)=05H聲明為5V編程電壓</p><p><b>　　編程接口：</b></p><p>　　采用控制信號(hào)的正確組合可對(duì)Flash閃速存儲(chǔ)陣列

32、中的每一代碼字節(jié)進(jìn)行寫入和存儲(chǔ)器的整片擦除，寫操作周期是自身定時(shí)的，初始化后它將自動(dòng)定時(shí)到操作完成。</p><p>　　看門狗（WDT）電路：</p><p>　　看門狗（WDT）電路的主要是實(shí)現(xiàn)復(fù)位功能。當(dāng)單片機(jī)運(yùn)行出現(xiàn)死循環(huán)時(shí),看門狗（WDT）電路可以起保護(hù)功能,實(shí)現(xiàn)復(fù)位作用。</p><p>　　Introduction of AT89C51</p&g

33、t;<p>　　Description:</p><p>　　The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufacture

34、d using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a

35、conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip</p><p><b>　　Features:</b></p><p>　　·Compatible with instruction se

36、t of MCS-51 products</p><p>　　·4K bytes of in-system reprogrammable Flash memory</p><p>　　·Endurance: 1000 write/erase cycles</p><p>　　·Data retention time: 10 years&

37、lt;/p><p>　　·Fully static operation: 0 Hz to 24 MHz</p><p>　　·Three-level program memory lock</p><p>　　·128×8-bit internal RAM</p><p>　　·32 progra

38、mmable I/O lines</p><p>　　·Two 16-bit Timer/Counters</p><p>　　·Six interrupt source</p><p>　　·Programmable serial channel</p><p>　　·Low-power idle a

39、nd Power-down modes</p><p>　　·On-chip oscillator and clock circuitry</p><p>　　·Full-duplex UART serial port interrupt line</p><p>　　·Dual Data Pointer Register</p&

40、gt;<p>　　Function Characteristic Description:</p><p>　　The AT89C51 provides the following standard features: 4K bytes of Flash memory, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a fiv

41、e vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two s

42、oftware selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt </p><p>　　The 8051 microcontroller is an industry standard architecture

43、that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure.

44、Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effect&l

45、t;/p><p>　　Pin Description:</p><p>　　·VCC: Supply voltage</p><p>　　·GND: Ground</p><p>　　·Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As

46、an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.</p><p>　　Port 0 may also be configured to be the multiplexed low order a

47、ddress/bus during accesses to external program and data memory. In this mode P0 has internal pull ups.</p><p>　　Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during

48、 program verification. External pull ups are required during program verification.</p><p>　　·Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull ups. The Port 1 output buffers can sink/

49、source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) be

50、cause of the internal pull ups.</p><p>　　Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p>　　·Port 2: Port 2 is an 8-bit bi-directional I/O

51、port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins t

52、hat are externally being pulled low will source current (IIL) because of the internal pull ups.</p><p>　　Port 2 emits the high-order address byte during fetches from external program memory and during access

53、es to external data memory which uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull ups when emitting 1s. During accesses to external data memory which uses 8-bit addresses (MOVX @ RI)

54、. Port 2 emits the contents of the P2 Special Function Register.</p><p>　　Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.</p><p

55、>　　·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs. When the P3 I write "1" after, they are internal pull-up is high,

56、and used as input. As input, due to the external pull-down for the low, P3 port output current (ILL) This is due to pull-up's sake.</p><p>　　Port 3 also serves the functions of various special features

57、of the AT89C51 as listed below:</p><p>　　Port 3 also receives some control signals for Flash programming and verification.</p><p>　　·RST: Reset input. A high on this pin for two machine cyc

58、les while the oscillator is running resets the device.</p><p>　　·ALE/: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the

59、 program pulse input () during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one A

60、LE pulse is skipped during each access to external Data Memory.</p><p>　　If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or

61、MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.</p><p>　　·：Program Store Enable is the read st

62、robe to external program memory. When the AT89C51 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memor

63、y.</p><p>　　·/ EA /VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however,

64、 that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. When / EA to maintain low, then during this period the external program memory (000

65、0H-FFFFH), regardless of whether an internal program memory.</p><p>　　This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.</p&g

66、t;<p>　　·XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p>　　·XTAL2：Output from the inverting oscillator amplifier.</p><p

67、>　　·Ready/: The progress of byte programming can also be monitored by the RDY/output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming

68、is done to indicate READY.</p><p>　　Oscillator Characteristics：</p><p>　　XTAL1 and XTAL2 respectively, reverse amplifier input and output. The reverse amplifier can be configured as on-chip osci

69、llator. Shi Jing oscillation and ceramic oscillation can be used. If using an external clock source drive the device, XTAL2 should not take. More than input to the internal clock signal through a two-way flip-flop, so th

70、e external clock signal pulse width without any request, but must ensure that the high-low pulse width requirements.</p><p>　　Clock Oscillator：</p><p>　　XTAL1 and XTAL2 are the input and output,

71、 respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used.</p><p>　　To drive the device from an external cloc

72、k source, XTAL2 should be left unconnected while XTAL1 is driven.</p><p>　　There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is thro

73、ugh a divide by two flip trigger, but minimum and maximum voltage high and low time specifications must be observed.</p><p>　　Idle Mode：</p><p>　　In idle mode, the CPU puts itself to sleep while

74、 all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by an

75、y enabled interrupt or by a hardware reset.</p><p>　　It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two mach

76、ine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected wr

77、ite to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that</p><p>　　Power-down Mode:</p><p>　　In the power-down mode, the osci

78、llator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and special function registers retain their values until the power-down mode is terminated. The only exit f

79、rom power-down is a hardware reset. Reset redefines the special function registers but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be h

80、eld active long enough to al</p><p>　　Programming the Flash:</p><p>　　The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready

81、to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside t

82、he user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with</p><p>　　The AT89C51 code memory array is programm

83、ed byte-by-byte in either programming mode. To program any nonblank byte in the on-chip Flash memory, the entire memory must be erased using the chip erase mode.</p><p>　　Programming Algorithm:</p>&l

84、t;p>　　Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table .To program the AT89C51, take the following steps:</p><p>　　1. In

85、put the desired memory location on the address lines.</p><p>　　2. Input the appropriate data byte on the data lines.</p><p>　　3. Activate the correct combination of control signals.</p>&

86、lt;p>　　4. Raise EA/VPP to 12V for the high-voltage programming mode.</p><p>　　5. Pulse ALE/once to program a byte in the Flash array or the lock bits. </p><p>　　The byte-write cycle is self-t

87、imed and typically takes no more than 1.5ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.</p><p>　　Data Polling:</p><

88、;p>　　The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write

89、cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data polling may begin any time after a write cycle has been initiated.</p><p>　　Program Verify:</p><p&g

90、t;　　If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits i

91、s achieved by observing that their features are enabled.</p><p>　　Chip Erase:</p><p>　　The whole array and three lock-bit PEROM electrical erase control signals through the right combination and

92、 maintain ALE pin is low 10ms to complete. Cleaning operation in the chip, code arrays were all written "1" and in any non-empty memory byte has been programmed to repeat the past, the operation must be execute

93、d. In addition, AT89C51 with steady-state logic, and can be in the low to zero frequency under the conditions of static logic, and supports two software selectable power-down mode. In</p><p>　　Reading the Si

94、gnature Bytes:</p><p>　　The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values retu

95、rned are as follows:</p><p>　　(030H) = 1EH indicates manufactured by ATMEL</p><p>　　(031H) = 51H indicates AT89C51 single-chip</p><p>　　(032H) = FFH indicates 12V programming</p&

96、gt;<p>　　(032H) = 05H indicates 5V programming</p><p>　　Programming Interface:</p><p>　　Every code byte in the Flash array can be written and the entire array can be erased by using the a

97、ppropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion.</p><p>　　Watchdog (WDT) circuit:</p><p>　　Wat